The advent of applications such as network computing, multimedia, video conferencing, and real-time imaging require data rates ranging into the gigabits-per-second. The demand for such high rates has led the industry to combine a standardized wide band network (SONET) with the simplicity of an efficient network that uses fixed-length 53-byte-wide asynchronous transfer-mode (ATM) cells. In 1992 ATM was chosen by the CCITT (Consultative Committee for International Telephony and Telegraphy and now the ITU) as the transport technology for the huge variety of services to be offered by the Broad band Integrated Services Digital Network (B-ISDN). However, it has been recognized that ATM is equally well-suited for use in the local area network. An ATM cell consists of 53 octets or bytes with a 5 byte cell header containing control bits and a 48 octet or byte cell payload which contains the data bits. In order to interface with a standardized wide band network, such as Synchronous Optical Network (SONET), appropriate interfaces to transfer from one system to the other have been and are being developed.
In order to integrate all of the functions of an ATM physical layer interface into a single device, and at the same time be applicable to local and wide area networking applications, a number of criterion have to be met. First, one requires a fully compliant SONET/SDH STS-3c framer. Here the term SDH refers to ITU's synchronous digital hierarchy and STS-3c refers to a data transmission rate of 155.52 megabits-per-second (Mbits/s) . The SONET STS-3c frame structure consists of 9 rows of bytes with each row having 9 bytes of transport overhead and 261 columns of 9 bytes each with one of the columns having control bits defining path overhead while the remaining columns are payload. The framer takes ATM cells and puts them into a synchronous series of SONET frames.
A second requirement of an interface device is an ATM cell processor to perform cell delineation and null cell insertion/filtering. Since many of the services elivered by ATM are by definition asynchronous, they are characterized by a non-continuous cell stream. Thus, cell rate de coupling transforms a non-continuous cell stream into a continuous stream by inserting idle or null cells (containing no payload) during idle periods in the assigned cell stream. By making the cell rate continuous, it is necessary only to synchronize with the incoming cells in order to place the ATM cells in their assigned locations in a frame.
A third requirement is a line side interface to support serial input/output at 155 Mbits/s. For SONET/SDH systems, current devices utilize expensive external phase locked loops and crystal oscillators to provide the clock recovery and clock synthesis functions. No one to date has been able to successfully implement integral phased locked loop circuits to recover clock and data from the encoded incoming data stream and to synthesize the high speed transmit clock from a low frequency reference.
Accordingly, it is an object of the invention to provide an integral phase locked loop that recovers the clock and data from the serial encoded receive stream and that synthesizes the high speed 155.52 MHz or 51.84 MHz transmit clock from a low frequency reference.